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Sunday, 16 December 2012

Members oh Members

i just realized that we're supposed to 'introduce' our bloggers lol


so....
here goes:




since this is kinda 'the end', 

kisses and hugs to you all out there who took the time to visit our blog xoxo

it has been an...experience ;p

the GPU @ VPU

example: the GeForce6600 GT


CHARACTERISTICS:
  • A specialized processor efficient at manipulating and displaying computer graphics
  • fundamental in 3D games
  • optimized for raster graphics

GPU COMPUTING
WHAT IS GPU Computing?

  • the usage of a graphic processing unit (GPU) along with a CPU to accelerate general-purpose scientific and engineering applications
  • pioneered by NIVIDIA

BASICALLY, a (GPU + CPU) combination is godlike because 
  • CPU consists of a few cores more suited for serial processing
  • while the GPU consists of thousands of smaller, more efficient cores suited for parallel processing
  • serial portions of codes are run on the CPU, while the parallel portions are run on the GPU
by Lua Xin Lin B031210345

Saturday, 15 December 2012

Computer Language : Usage of Syscall


Input / Output : Usage of Syscall

·         Assembly programs request a service by loading the system call (syscall) instruction.



Format  :


·        System services.
Service
System Call Code
Arguments
Result
print_int
1
$a0 = integer
print_float
2
$f12 = float
print_double
3
$f12 = double
print_string
4
$a0 = string
read_int
5
integer (in $v0)
read_float
6
float (in $f0)
read_double
7
double (in $f0)
read_string
8
$a0 = buffer, $a1 = length
sbrk
9
$a0 = amount
address (in $v0)
exit
10
print_character
11
$a0 = character
read_character
12
character (in $v0)
open
13
$a0 = filename,
file descriptor (in $v0)
$a1 = flags, $a2 = mode
read
14
$a0 = file descriptor,
bytes read (in $v0)
$a1 = buffer, $a2 = count
write
15
$a0 = file descriptor,
bytes written (in $v0)
$a1 = buffer, $a2 = count
close
16
$a0 = file descriptor
0 (in $v0)
exit2
17
$a0 = value

Example :
a.) exit


b.) Get a number and store it


c. ) Print result from $t2


By : Wong Poh Ling    B031210033

Computer Language : Logical Operation


Logical Operation



Logical
and
and $1,$2,$3
$1 = $2 & $3
3 register operands; Logical AND
or
or $1,$2,$3
$1 = $2 | $3
3 register operands; Logical OR
not
nor $1,$1,$0
0=1/ 1=0
convert 1 to 0
convert 0 to 1
and immediate
andi $1,$0,100
$1 = 100
Logical AND register, constant
or immediate
ori $1,$0,100
$1 =100
Logical OR register, constant
shift left logical
sll $1,$2,10
$1 = $2 << 10
Shift left by constant
shift right logical
srl $1,$2,10
$1 = $2 >> 10
Shift right by constant

·         Example :   1.)                  sll   $t0,$t0,16                     srl   $t0,$t0,24
 0001 0010 0011 0100 0101 0110 0111 1000

solution : 
0101 0110 0111 1000 0000 0000 0000 0000      #sll
0000 0000 0000 0000 0000 0000 0101 0110      #srl


2.)         if     $t1 contains    00000000 00000000 00000000 00101100
                    $t2  contains   00000000 00000000 00000000 00001010

                What is the final content of $8 after this instruction is performed?
1.        and  $t0, $t1, $t2          # reg  $t0 = $t1 & $t2
2.        or   $t0, $t1, $t2          # reg  $t0 = $t1 & $t2

Solution:
For the AND operation, $t0 contains
      00000000 00000000 00000000 00001000
For the OR operation, $t0 contains
      00000000 00000000 00000000 00101110

By : Chong Cai Ning      B031210080

HAZARDS (Pipelining)


  •   Hazards are problems with the instruction pipeline in CPU micro architecture that potentially result in incorrect  computation.


·              There are three types of hazards:
Ø  Data Hazard:
o   Occurs when instructions exhibit data dependence modify data in different stages of a pipeline.

o   There are three situations in which the data hazards can occur:
§  Read after write (RAW)-true dependency
§  Write after read (WAR)-anti-dependency
§  Write after write (WAW)-output dependency

o   RAW:
§  A situation where an instruction refers to a result that has not been yet calculated or retrieved
§  Occurs when an instruction is executed after a previous instruction has not yet been completely processed through the pipeline.
§  Eg:
ü  I1.R2<- R1+R3
ü  I2.R4<- R2+R3
ü  First instruction (i1)is calculating a value to be saved in register R2 and second instruction is going use that value to compute a result for register R4
ü  However, in pipeline, when we fetch the operand for the 2nd operation, result from the first is not yet been saved and hence we have data dependency…

 
Diagram for data hazards…
o   WAR
§  Occur when instruction 2 tries to write destination before it is read by instruction 1.
§  Represent a problem with concurrent execution.
§  Eg:
ü  I1.R4 <- R1+R3
ü  I2.R3<- R1+R2
ü  If I2 is completed earlier than I1 ,ensure that do not store the result of register R3 befreI1 has had a chance to fetch an operand.

o   WAW
§  I2 tries to read write an operand before written by I1
§  May occur in concurrent execution environment
§  Eg:
ü  I1.R2<- R3+R4
ü  I2.R2<- R1+R2
ü  Delay the WB(Write Back) of I2 until the execution of I1…
o   There are 3 ways to handle the data hazards:
o   Software: insert independence instruction(or no-ops)
o   Hardware: insert bubbles (stall the pipeline)
                   :data forwarding

Diagram of handling data hazards through software…

Diagram of handling data hazards through hardware(insert bubbles/stall the pipeline)…
Note: Pipeline stall
          To insure proper pipeline execution in light of register dependences, we must:
1.      Detect the hazards
2.      Stall the pipeline:
--prevent IF (do not want to lose any instructions) and ID (can’t continue until the dependent instruction complete correctly) stages from making progress
=do not write the PC (PCWrite=0);
=do not rewrite IF/ID register (IF/IDWrite =0);
 --inserts “no-ops” into later stages
=set all control signals propagating to EX/MEM/WB=0;

Diagram of eliminating data hazards via forwarding with stalling pipeline after loading….
Note:
Data forwarding…
=forwarding handles 2 types of data hazards which are EX HAZARDS & MEM HAZARDS.
=The third type hazards (WB HAZARDS)is already handled by using a transparent reg file in which this reg file allow the write data to be forwarded to the output if the register file is asked to read and write the same register in the same cycle…
=Forwarding method only is NOT enough to eliminate all the data hazards therefore it must works with pipeline stall just like the diagram shown above.
Ø  Structural Hazards…
o   Occur when a part of processor’s hardware is needed by two or more instructions at the same time.
o   Eg:
o   A memory unit that is accessed both in the fetch stage where data is written and/or read from memory.
o   Can be resolved by :
o   Separating the component into orthogonal unit (eg: separate cache)
o   Bubbling the pipeline


Diagram of resolving structural hazards via bubbling the pipeline…

Ø  Control hazards (branch hazards)
o   Occurs with branches
o   Can cause greater performance lost than data hazards
o   When a branch is executed it may or may not change the PC (to other value than its value+4)
o   It is said taken branch if the branch is changing to its target address and vice versa…
o   If the instruction I is a taken branch, then the value will not change until the end of MEM stage of the instruction execution in the pipeline
o   A branch causes 3 cycle stall in processor pipeline:
=One cycle repeated IF (IF is redundant if branch is not taken)
=Two idle cycle
o   The three clock cycle lost for every branch is a significance loss and the machine with branch stall with 30% branch frequency   only achieve half of the speedup of pipelining
o   Reducing the branch penalty becomes critical…
o   To avoid the control hazards :
=insert pipeline bubble which guaranteed to increase latency
=use branch prediction and make educated guesses about which instruction to insert



Chong Cai Ning

B031210080