PSEUDO-DIRECT ADDRESSING

e)      Pseudo-Direct Addressing

I)                   The memory address is (mostly) embedded in the instructions.

II)                Speciafically used for J-type instructions, j and jal.

III)             Effective address is calculate by taking the upper 4 bits of the PC, concatenated to the 26 bits immediate value, and the lower 2 bits are 00.

IV)             The new effective address will always be word-aligned and we can never have a target address of a jump instruction with 2 bits.

*Word-aligned means that an address (unless you use one of the special instructions for loading or storing bytes) must be a multiple of 4.

*An address that isn’t multiple of 4 can lead to undesirable results.

BY WONG POH LING

B031210033

PC-RELATIVE ADDRESSING

d)      PC-Relative Addressing

I)                   A data or instruction memory location is specified as an offset relative to the incremented PC.

II)                It usually used in condition branches. PC refers to special purpose register, Program Counter that stores the address of next instruction to be fetched.

III)             The offset value can be an immediate or an interpreted label value.

IV)             The effective address is the sum of the Program Counter and offset value in the instruction. It determines the branch target.

V)                This addressing inplements position-independent codes. Only a small offset is adequate for shorter loops.

BY CHONG CAI NING

B031210080

BASE ADDRESSING

c)      Base Addressing

I)                   A data or instruction memory iocation is specified as a signed of set from a register.

II)                A register act as a pointer to an operand located at the memory location whose address is in the register.

III)             The register is called base that may point to a structure or some other collection of data an immediate value is loaded at a constant offset from the beginning of the structure.

IV)             The offset specifies how far the location of the operand data from the memory location pointed by the base.

V)                Address of operand = offset value + base value (rs). However, the size of operand is limited to 16 bits because each MIPS instruction fits into a word.

VI)             Offset value is a signed number which is represented in a 2’s complement format. Therefore, offset value can also be a negative value.

BY CHONG LEE MAN

B031210367

IMMEDIATE ADDRESSING

b)      Immediate Addressing

I)                   A numeric value embedded in the instruction is the actual operand.

II)                Operand is constant within the encoded instruction.

III)             Executed faster in comparison with other addressing mode because not involved memory access.

IV)             Destination held in the instruction.

BY KU MAN YI

B031210161

REGISTER ADDRESSING

ADDRESSING MODES

l  The way of specifying an operand or a memory address.

a)      Register Addressing

I)        A source or destination operand is specified as content of one of the registers

$ 0 - $ 31.              

II)                Both operand are in register form.

III)             Executed faster in comparison with other addressing mode because not involved memory access.

BY LUA XIN LIN
B031210345

MIPS, I-TYPE

iv.              sw  rt,  imm (rs) [store, I-type]

ALU Usage :

1)      PC update                        :  no update beyond the normal increment

2)      Source operand fetch        :  rs and the sign extended immediate field

*The rt register is also fetched

3)      ALU operation                  :  the source operand are added to get the memory address

4)      Memory access                  :  a memory write control signal is sent to memory

*The result from the ALU is sent to memory as the address

*The contents of rt are sent to memory as the write data

5)      Register write                    :  none

v.              beq  $rs,  $rt,  imm [register jump, R-type]

ALU Usage :

1)      PC update                        :  jr and jalr :  PCß rs

2)      Source operand fetch        :  rs

3)      ALU operation                  :  none

4)      Memory access                  :  none

5)      Register write                    :  jr : there is no register write

  jalr : rd ß PC + 4

*For jalr, the incremented PC value must be capture before the target address is placed into the PC. With edge-triggered clocking this is easy to do. There is an adder to produce the PC + 4 values. Since the PC does not change until the start of the next cycle, the adder output will not change until the start of the next cycle

vi.              jal  target [non-register jump, R-type]

ALU Usage :

1)      PC update                        :  jr and jalr :  PCß target address

*The target address is concatenation of the high order 4 bits of PC + 4, the target field of the instruction, and two 0 bit

2)      Source operand fetch        :  none

3)      ALU operation                  :  none

4)      Memory access                  :  none

jr : There is no register write

jal : ra ß PC + 4

*For jal, the incremented PC value must be capture before the target address is placed into the PC. With edge-triggered clocking this is easy to do. There is an adder to produce the PC + 4 values. Since the PC does not change until the start of the next cycle, the adder output will not change until the start of the next cycle.

BY WONG POH LING

B031210033

MIPS, I-TYPE

 ALU Usage :

1)        PC update                                   :  no update beyond the normal increment

2)        Source operand fetch :  rs and rt

3)        ALU operation                 :  determined by the function (funct) field

4)        Memory access                 :  none

5)        Register write                   :  result from ALU written to rd

31                   26	25                   21	20                   16	15                    0
op	rs	rt	immediate

Example :

i.              addi  rt,  rs,  imm [immediate, I-type]

ALU Usage :

1)      PC update                        :  no update beyond the normal increment

2)      Source operand fetch        :  rs and immediate field

*For all instruction except sltiu the immediate field is sign extended.

*For sltiu the immediate field is 0 extended.

3)      ALU operation                  :  determined by the opcode

4)      Memory access                  :  none

5)      Register write                    :  result from ALU written to rt

ii.              beq  $rs,  $rt,  imm [branch, I-type]

ALU Usage :

1)      PC update                        :  if the branch condition is true,

PCß PC + 4 + (sign-extended immediate) << 2

2)      Source operand fetch        :  rs and rt

3)      ALU operation                  :  the source operand are subtracted for comparison

4)      Memory access                  :  none

5)      Register write                    :  none

iii.              lw  rt,  imm (rs) [load, I-type]

ALU Usage :

1)      PC update                        :  no update beyond the normal increment

2)      Source operand fetch        :  rs and the sign extended immediate field

3)      ALU operation                  :  the source operand are added to get the memory address

4)      Memory access                  :  a memory read control signal is sent to memory

*The result from the ALU is sent to memory as the address

5)      Register write                    :  the data from memory is written to rt

BY CHONG LEE MAN

B031210367

MIPS, I-TYPE / J-TYPE

B.       Immediate type

l  Include instruction with :

1.        Immediate operand

2.        Branch instructions

3.        Load and store instruction

l  All opcodes except 000000, 00001x, and 0100xx are used for this instruction.

bits	6	5	5	16
Instructions syntax	Operation code (op)	Source register specifier (rs)	Target register specifier or branch condition (rt)	Immediate, branch displacement or address displacement (immediate)

Example :

lw  $t0 , 1200($t1)

35	9	8	-1200
100011	01001	01000	0000010010110000

Decimal representation

Binary representation  

C.       Jump type

l  Two direct jump instructions (j and jal).

l  Require a memory address to specify their operand

l  Opcodes 00001x

bits	6	26
Instructions syntax	Operation code (op)	Target address (target)

INSTRUCTION TYPE APPLICATION

31             26	25           21	20           16	15           11	10            6	5             0
op	rs	rt	rd	shamt	funct

Example :

i.              add  rd,  rs,  rt [non-jump R-type]

ii.              jalr  rd,  rs [jump register, R-type)
BY LUA XIN LIN
B031210345

MIPS, INTRO / R-TYPE

INTRODUCTION

l  MIPS have a small number of ways that is computes addresses in memory.

l  It can be address of an instruction or a data.

l  Instruction format means how an instruction is put together.

l  Addressing mode means how to determine the address of an operand.

INTRUCTION FORMATS

A.      Register type

l  Do not require :

1.        An immediate value

2.        Target offset

3.        Memory address displacement

4.        Memory address to specify an operand

l  Include arithmetic and logic with all operand in registers, shift instructions, and register direct jump instructions(jal and jr).

l  All are type instructions use opcode 000000.

bits	6	5	5	5	5	6
Instructions syntax	Operation code (op)	Source register specifier (rs)	Target register specifier (rt)	Destination register specifier (rd)	Shift amount (shamt)	Function field (funct)

Example : 

add  $t0 , $s1 , $s2

0

$s1

$s2

$t0

0

add

0

17

18

8

0

32

000000

10001

10010

01000

00000

100000

 by CHONG CAI NING 

B031210080