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In computing, pipelining is a set of data processing elements
connected in series therefore the output of one element is the input of the
next element.
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The above statement means the microprocessor begins to
execute second instruction before the first instruction complete.
·
The pipeline is divided into segments and each segment
can execute its operation concurrently with the other segments.
·
That is , when a segment complete an operation, it
passes the result to the next segment in pipeline & fetches the next
operation from the preceding segment.
·
For a microprocessor that without the pipelining, the
second operation will only started when the first operation fully completed.
·
Therefore, the microprocessor which with the
pipelining will be more efficient and faster compared to the one without
pipelining…
·
Below is a diagram of microprocessor with a
pipelining…
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for 4 loads:
Ø 8/3.5 or
(4(4)/(4+3))=2.3
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Non-stop:
Ø 4n/(n+3)=4(16)/(16+3)=3.347≈4
stages
·
Although the pipelining initially formerly a feature
only of high-performance & RISC-based microprocessor, now is commonly in
microprocessor used in personal computers. (For examples, Intel’s Pentium uses pipelining to execute as
many as six instructions simultaneously….)
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Besides, pipelining also called pipeline processing.
·
Eg:
Ø DRAM:
o Memory loads
the requested memory contents into small cache composed of SRAM and then
immediately begins fetching the next memory.
o Creates two
stages:
§ Stage1: data
is read from or written to the SRAM
§ Stage2:data
is read from or written to memory
Ø DRAM(c’td):
o Usually
combine with another performance technique called burst mode
o And the two
techniques together called pipeline burst cache
·
MIPS Pipelining:
o Five stages
(one step per stage):
o IF:
instruction fetch from memory
o ID:
instruction decode and register read
o EX: execute
operation or calculate address
o MEM: access
memory operand
o WB: write
result back to register
Chong Lee Man
B031210367
