MIPS, I-TYPE

iv.              sw  rt,  imm (rs) [store, I-type]

ALU Usage :

1)      PC update                        :  no update beyond the normal increment

2)      Source operand fetch        :  rs and the sign extended immediate field

*The rt register is also fetched

3)      ALU operation                  :  the source operand are added to get the memory address

4)      Memory access                  :  a memory write control signal is sent to memory

*The result from the ALU is sent to memory as the address

*The contents of rt are sent to memory as the write data

5)      Register write                    :  none

v.              beq  $rs,  $rt,  imm [register jump, R-type]

ALU Usage :

1)      PC update                        :  jr and jalr :  PCß rs

2)      Source operand fetch        :  rs

3)      ALU operation                  :  none

4)      Memory access                  :  none

5)      Register write                    :  jr : there is no register write

  jalr : rd ß PC + 4

*For jalr, the incremented PC value must be capture before the target address is placed into the PC. With edge-triggered clocking this is easy to do. There is an adder to produce the PC + 4 values. Since the PC does not change until the start of the next cycle, the adder output will not change until the start of the next cycle

vi.              jal  target [non-register jump, R-type]

ALU Usage :

1)      PC update                        :  jr and jalr :  PCß target address

*The target address is concatenation of the high order 4 bits of PC + 4, the target field of the instruction, and two 0 bit

2)      Source operand fetch        :  none

3)      ALU operation                  :  none

4)      Memory access                  :  none

jr : There is no register write

jal : ra ß PC + 4

*For jal, the incremented PC value must be capture before the target address is placed into the PC. With edge-triggered clocking this is easy to do. There is an adder to produce the PC + 4 values. Since the PC does not change until the start of the next cycle, the adder output will not change until the start of the next cycle.

BY WONG POH LING

B031210033