= Is a part of
the processor (CPU) that performs arithmetic
and logical operations on the operands in computer instruction words.
=Below is the picture of the Arithmetic & Logic
Unit (ALU);
= There are 2 types of instructions performed by ALU:
a.
Arithmetic Instruction:
o
Adding
o
Subtraction
o
Shifting operations
b.
Logic Instruction:
o
Boolean comparisons (AND , OR, XOR
and NOT operations)
=In some processors, the ALU is divided into 2 units :
Arithmetic Unit (AU), Logic Unit (LU)
= ALU:
·
Designed to perform integer
calculations ( Eg: adding and subtraction)
·
Often can handle multiplication
between 2 integers as:-
o
the result is integer
·
Do not perform division as:-
o
The result may be fraction or “floating
point “ number
=There are few types of ALU with different bits, for
examples 1-bit ALU .
= 1-bit ALU:
§
The diagram of 1-bit logic unit for
AND and OR is as below:
o
Based on the diagram above,
the multiplexer on the right side select either a AND b or a OR b depending
on whether the value of operation is 0 or 1…
>>>multiplexor
o
Below is the 1-bit adder…
v Also called a (3,2) adder as there
is…
ü 3 inputs and 2 outputs
( if only input
a and b ,this adder will be (2,2)
adder or half
adder ….[2 input , 2 output])
v The CarryOut is the second output
pass on the carry
v CarryIn is the third input as
CarryOut from the neighbor adder must be
included…
v
o
Then
lets us see the Input and Output specification for 1-bit adder as below…
ü From the truth table above we can
express the CarryOut and Sum into the logical unit as below…
CarryOut=(b.CarryIn)+
(a.CarryIn)+(a.b)+(a.b.CarryIn)
Simplified into…
CarryOut=(b.CarryIn)+(a.CarryIn)+(a.b)
(Note : If (a.b.CarryIn)
is true, all other three terms must be
true and so the last term can be leaving out corresponding to the 4th
line of the table…)
ü Then we will get a truth table like
below…
INPUTS
|
||
a
|
b
|
CarryIn
|
0
|
1
|
1
|
1
|
0
|
1
|
1
|
1
|
0
|
1
|
1
|
1
|
ü And the hardware within the black
box for CarryOut consists of 3 AND gates (correspond exactly to
the 3 parenthesized term:[a.CarryIn],[b.CarryIn],[a.b]) and 2 OR gates
(sum up all the parenthesized term)…
ü The adder hardware for CarryOut
signal is as below…
Ø Sum bits is set when…
Ø At least one input is 1 or
Ø All three inputs are 1
ü Results in complex Boolean Equation …
Sum=
(a.b’.CarryIn’)+(a’.b.CarryIn’)+(a’.b’.CarryIn)+(a.b.CarryIn)
ü Finally combining the adder and the
1-bit logic unit for AND and OR gates and we will obtain diagram…
v From the diagram above …
=the
multiplexor controlled by the operation line is expanded and 0 is connected directly to the
new input of the expanded multiplexor by adding an operator…
(This
is the easiest way to allow ALU perform
more simplest operations, eg: generating 0)
=32-bits ALU
·
A
32-bits ALU can be constructed from 32 1-bit ALU just like diagram below…
Chong Cai Ning B031210080
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